The present invention relates to high-voltage switching circuits of nonvolatile memory devices and more particularly, to a high-voltage switching circuit shortening a boosting time of a drive signal activating a high-voltage switch.
In nonvolatile memory devices such as flash memories or EEPROMs, a high voltage (VPP) is needed for programming or erasing operations relative to other memory devices. The high voltage is internally generated and has a higher voltage than an external power source voltage (VCC). A high-voltage switch is required to switch to the high voltage VPP or to transfer the high voltage to a wordline. And, when the high-voltage switch includes an NMOS transistor, the high-voltage switch needs a voltage higher than the high voltage VPP that is applied to a gate of the NMOS transistor. For this, a boosting circuit for boosting the gate of the NMOS transistor may be required for the high-voltage switch.
FIG. 1 is a circuit diagram illustrating a conventional high-voltage switching circuit, including a high-voltage switch 11, a boosting enable unit 12, and a high-voltage switching booster 13.
Referring to FIG. 1, the high-voltage switch 11 includes an NMOS transistor N1 that transfers the high voltage VPP as an output signal VPPOUT, activated by a drive signal (i.e., a signal of a node NB) provided from the high-voltage switching booster 13.
The boosting enable unit 12 includes inverters IV1 and IV2, and an NMOS transistor N2, activating the high-voltage switching booster 13 in response to an enable signal EN.
The high-voltage switching booster 13 is provided to boost the drive signal (i.e., the signal of the node NB) for activating the high-voltage switch 11, high-voltage switching booster 13 including two capacitors Ca and Cb, and two NMOS transistors N3 and N4. NMOS transistor N2 is configured in the form of diode connection. The capacitors Ca and Cb respond respectively to clock signals CK and CKB, where clock pulse CKB is the inverse of clock pulse CK.
FIG. 2 illustrates waveforms of opposite clock signals CK and CKB, and FIGS. 3A through 3C illustrate an operation of the high-voltage switching booster 13 shown in FIG. 1. Hereinafter, the operation of the high-voltage switching booster 13 will be described with reference to FIGS. 2, and 3A through 3C.
The simplest way for boosting a signal or a node is to utilize the clock signals CK and CKB. As shown in FIG. 3A, one electrode of the capacitor Ca is coupled to the clock signal CK while the other electrode of the capacitor Ca is connected to the node NA. One electrode of the capacitor Cb is coupled to the clock signal CKB while the other electrode of the capacitor Cb is connected to the node NB. Thus, the nodes NA and NB are changed whenever the clock signals CK and CKB vary. Here, Cs represents a parasitic capacitance of the node NB.
First, as shown in FIG. 3A, when the clock signal CK is 0V while the clock signal CKB is VCC (refer to FIG. 2), the capacitor Ca does not conduct a pumping operation while the capacitor Cb conducts a pumping operation. Then, the NMOS transistor N3 is turned on while the NMOS transistor N4 is turned off. Thus, the node NB is boosted up to Vb through the pumping operation by the capacitor Ca. Then node NB decreases to Vb−Vth1 by a threshold voltage Vth1 of the NMOS transistor N3 because node NB is connected to the gate of the NMOS transistor N3.
Next, as shown in FIG. 3B, if the clock signal CK turns to Vcc from 0V while the clock signal CKB turns to 0V from Vcc, the capacitor Ca starts to pump charges while the capacitor Cb does not conduct the pumping operation. Then, the NMOS transistor N3 is turned off while the NMOS transistor N4 is turned on. Thus, the node NA is boosted up to Vb−Vth1+Vcc from Vb−Vth1 by the pumping operation. As a gate of the NMOS transistor N4 is coupled to the node NA, the node NB decreases to Vb−Vth1+Vcc−Vth2 by a threshold voltage Vth2 of the NMOS transistor N4.
And, as shown in FIG. 3C, if the clock signal CK turns to 0V from Vcc while the clock signal CKB turns to Vccc from 0V, the capacitor Cb starts to pump charges again while the capacitor Ca does not conduct the pumping operation. Then, the NMOS transistor N3 is turned on while the NMOS transistor N4 is turned off. Thus, the node NB is boosted up to Vb−Vth1+Vcc−Vth2+rVcc, where r=Cb/(Cb+Cs), from Vb−Vth1+Vcc+Vth2 by the pumping operation.
Here, the maximum voltage gain at the node NB is Vb−Vth1+Vcc−Vth2+rVcc. A practical voltage gain at the node NB is lower than the maximum gain because the NMOS transistor N4 is diode-coupled therein. Thereby, a gate voltage of NMOS transistor N4 is affected from the voltage of node NA, node A decreasing when the voltage level of the node NA falls down.
Accordingly, problems may occur when a voltage level transferred to the node NB, i.e., a charge amount (a source voltage of NMOS transistor N4), becomes lower as time progresses as illustrated in FIG. 4.
As a result, a time for transferring the high voltage VPP as an output signal by the high-voltage switch 11 increases as shown in FIG. 5, which increases even more as the power source voltage Vcc becomes lower.